Testing of electronic circuits

ABSTRACT

A plurality of integrated circuits that are used in an electronic circuit have functional interconnections and dedicated test connections. The integrated circuits receive and transmit synchronization information, such as clock signals from one integrated circuit to another successively through the chain. This permits a high-test speed. Preferably the synchronization information is serialized with test data, test results and/or commands. Preferably, the bit rate between successive integrated circuits in the chain is programmable by means of commands transmitted through the chain. Thus, different bit rates may be at different locations along the chain to reduce the delay occurred by the synchronization signals along the chain.

BACKGROUND OF THE INVENTION

U.S. Pat. No. 5,606,566 describes a circuit test technique that uses theIEEE1149.1 test standard. A circuit contains a plurality of integratedcircuits with functional interconnections to communicate signals betweenthe integrated circuits during normal operation. The circuit is testedby entering test signal into the circuit and observing how the circuitresponds to the test data. The interconnections between the integratedcircuits, for example, are tested by applying test signals at the outputof the integrated circuits and observing whether corresponding responsesignals arrive at the inputs of the integrated circuits.

The IEEE1149.1 standard, as described in U.S. Pat. No. 5,606,566 definesa test interface for entering the test signals into the circuit andreading the response signals from the circuit. A one-bit wide shiftstructure is used for this purpose. The integrated circuits areconnected in a chain of successive integrated circuit. Each integratedcircuit has one test data input terminal coupled to its predecessor inthe chain, if any, and one test data output coupled to its successor inthe chain, if any. In addition the integrated circuits have test clockand test mode select inputs coupled in common.

Successive bits of the test signals are applied to the test data inputof the chain and shifted from integrated circuit to integrated circuitin the chain to the integrated circuit from where the test signal isoutput to test the functional interconnections. Similarly, the responsesignals are loaded into the integrated circuit from the functionalinterconnections and successive bits of the response signals are shiftedfrom integrated circuit to integrated circuit in the chain to a testdata output. Control instructions are similarly shifted through thechain. Shifting, outputting and loading is synchronized by a centralclock that is coupled to the test clock inputs of the integratedcircuits and controlled by a mode select signal that is coupled to thetest mode select inputs of the integrated circuits. The mode selectsignal controls how the test interface traverses a state diagram of thetest interface.

The IEEE1149.1 standard is based on a compromise between access speedand pin/connection count. Only two test data pins are needed perintegrated circuit, and only one test data connection to anotherintegrated circuit. In return, it takes a long time to write or readtest data, because the data and instructions have to pass through achain of integrated circuits.

Various techniques have been proposed to increase the access speed ofIEEE1149.1 interfaces U.S. Pat. No. 5,606,566, for example, proposes touse several chains in parallel. A method of improving speed is of courseto increase the speed of the test clock. But there are limits to themaximum clock speed, not only in terms of maximum internal speed of theintegrated circuits, but also due differences between the delaysintroduced by the connections from the central clock source to thedifferent integrated circuits. The differences between these delays arereferred to as clock skew. These should not exceed the length of theclock period.

SUMMARY OF THE INVENTION

Among others, it is an object of the invention to realize a high clockspeed in a test interface of a circuit.

Among others, it is an object of the invention to reduce the time neededfor testing circuits.

The invention provides for a system according to claim 1. A chainconnection between the integrated circuits is used for communicatingtest information to test functional interconnections between differentintegrated circuits. According to the invention synchronizationinformation, such as a test clock signal, that determines when test datais output by the integrated circuits to the functional interconnectionsand captured from the functional interconnections by the integratedcircuits is transmitted through the chain from one integrated circuit toanother. This eliminates problems due to discrepancies between the delayof arrival of the test synchronization information and the test data atthe integrated circuit. Preferably all integrated circuits in the chainreceive their synchronization information, such as clock signals,through the chain, but without deviating from the invention furtherintegrated circuits may be added that receive a central synchronizationinformation, be it from the tester, for example when these furtherintegrated circuit are at the front of the chain, or from a localsynchronization information supply circuit for a plurality of successivecircuits in the chain, where the local synchronization information isderived from clock signals received via the chain.

Preferably the integrated circuits replace test data, which initiallytravels with synchronization information at the input of the chain, bytest results that travels with that synchronization information to theoutput of the chain. Thus, the amount of time needed to perform a testis reduced. Also preferably, the synchronization information includesstate selection information common for all integrated circuits in thechain. In this case, the integrated circuits in the chain are eacharranged to step through a series of states, wherein successive statesare selectable under control of the synchronization informationindiscriminately for all integrated circuits in the chain. Reachingparticular states triggers update and capture. The state diagram definedfor the IEEE1149.1 standard may be used for example. Thus, theintegrated circuits in the chain collectively can flexibly adapt thesequence of states.

Preferably, a tester coupled to the chain ensures that the rate at whichthe synchronization information is updated is so low that all integratedcircuits in the chain receive synchronization information that causes anupdate of the test signals applied to the functional interconnectionbefore a first integrated circuit in the chain receives synchronizationinformation that causes a capture. The tester may for example determinethe required delay on the basis of information about the integratedcircuits in the chain, but preferably the tester measures whethersynchronization that causes the update has arrived at the end of thechain and transmits the synchronization information that causes theupdate only after such a measurement.

Preferably, the synchronization information is transmitted temporally inseries with the test data, test results and/or commands through a samecommunication conductor from one integrated circuit to another. Thus aminimum of connecting pins has to be provided for test purposes anddifferent skew is avoided. Preferably a pair of pins is used betweeneach pair of integrated circuits to transmit the information as adifferential signal. This increases the maximum possible speed. Inaddition, it makes it possible to use integrated circuits with mutuallydifferent supply voltages.

In an embodiment the integrated circuits receive and transmit successivewords that contain the synchronization information temporally in serieswith the test data, test results and/or commands. The integratedcircuits copy the synchronization information received from a receivedword to a transmitted word and replace a received bit of the test data,test results and/or commands from the received word in the transmittedword by an internal bit of the test data, test results and/or commands,produced in the integrated circuit. The internal bit is for example abit of test data or a test result from an earlier word that has traveledthrough the integrated circuit or a test result that has been capturedin the integrated circuit. Thus, a minimum transmission delay isrealized for the synchronization information (and thereby a maximum testspeed), while permitting processing of test data in the integratedcircuit.

In a further embodiment at least one of the integrated circuit comprisesa test controller circuit is connected to the chain via a shell thatmakes it appear as if the serially transmitted bits of synchronizationdata and test data, test results and/or commands arrive in parallel.Thus, a conventional test controller, such as an IEEE1149.1 tapcontroller may be used in combination with chained transmission of clocksignals.

In another embodiment, the words that contain the synchronization andtest data contain additional positions for programming information forselected integrated circuits in the chain. For example, the programminginformation may be used to supply successive edges in write enablesignals for a programmable memory, following n words (n=16 for example)in which test data has been supplied that serves as information that hasto be written in parallel into the memory.

In an embodiment at least part of the integrated circuits allows forprogrammable bit rates of reception and transmission of test data andsynchronization information. Initially the bit rates are set to apredetermined value in an initial state. But the bit rates arereprogrammed under control of an integrated circuit specific commandreceived via the chain. Integrated circuits in the circuit under testmay have different maximum possible speeds. Dependent on the circuitunder test, successive integrated circuits in the chain may have thesame maximum possible speeds or different maximum possible speeds. Atester has information about the successive integrated circuits in thechain and their maximum possible speeds. Initially all integratedcircuits use a predetermined bit rate that is acceptable for all.Afterwards the tester may set the bit rate to different values atdifferent points along the chain, as maximally permitted betweensuccessive pairs of integrated circuits. Thus, the delay experienced bythe synchronization information is minimized, which maximizes testspeed.

In an embodiment integrated circuits in the chain have of said at leastpart of the integrated circuits each have an external clock inputterminal for initially clocking transfer of data along the chain from acentral clock to which all clock input terminals are coupled in common.In this case, a command may be supplied to switch to chainedtransmission of synchronization information, such as the clock signal,at a much higher bit rate.

In another embodiment integrated circuits of the chain have externalreset input terminals coupled in common to a central reset input toreset to the bit rate that is acceptable for all integrated circuit.

BRIEF DESCRIPTION OF THE FIGURES

These and other objects and advantageous aspects of the invention willbe described in more detail using the following figures.

FIG. 1 shows a test system.

FIG. 2 shows an integrated circuit.

FIG. 3 shows an integrated circuit with a programmable memory.

FIG. 3 a shows an integrated circuit with a programmable memory.

FIG. 4 shows an integrated circuit with partially independent clockcircuits.

FIG. 4 a shows an integrated circuit with partially independent clockcircuits.

FIG. 5 shows an integrated circuit.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 shows an embodiment of a test system. The system contains atester 10 and a circuit under test 11. Circuit under test 11 contains anumber of integrated circuits 12, 14 interconnected by some functionalinterconnection circuit 16. For test purposes integrated circuits 12, 14are also connected in a chain that has an input 18 coupled to an outputof tester 10 and an output 19 coupled to an input of tester 10. Theconnections between pairs of successive integrated circuits 12, 14 inthe chain are communication connections for transmitting a single bit ata time, e.g. each a single conductors or a pair of conductors used fordifferential signal transmission.

In normal operation circuit 11 is not connected to tester 10. In normaloperation functional circuits in integrated circuits 12, 14 performvarious functions for which circuit 11 has been designed and communicateinformation via functional interconnect circuit 16. Generally speaking,functional interconnect circuit 16 includes a set of conductor linesthat provide for point-to-point connections between terminals ofintegrated circuits 12, 14 (plus optionally some glue logic). In generalthese connections do not follow the chain-like nature of the test chain:functional interconnect circuit 16 may an integrated circuits at anypositions along the chain and often an integrated circuits will haveinputs and/or outputs connected to several other integrated circuits,not just one such as in the chain.

In order to test circuit 11 it is connected to tester 10. Tester 10enters test data into the integrated circuits 12, 14 and reads responsesto this test data as test results from the integrated circuit. Beforeand after the actual test the test, data and results enter and leave thecircuit 11 along the chain, i.e. along a path that is independent of thefunctional interconnection circuit 16. In particular the functionalinterconnection circuit does not generally have the same chainstructure. Hence it is not generally the case that, when a test signalarrives at a first integrated circuit after transmission from a secondintegrated circuit through the chain, all functional signals will travelthrough functional interconnection circuit from the first integratedcircuit to the second integrated circuit as well and with the samedelay. On the contrary, some functional signals may travel in theopposite direction and with different transmission delays.

Typically, circuit under test 11 also comprises a carrier (not shown),such as a printed circuit board on which functional connections 16, aswell as the connections for the test chain, are implemented and to whichthe integrated circuits are attached. In this case, testing is used totest functionality of the circuit on the carrier. In other circumstancescircuit 11 under test may comprise an interconnected system of aplurality of such carriers.

One of the integrated circuits 14 is shown in more detail (the otherintegrated circuits 12 may have a similar structure). Integrated circuit14 contains a receiver 140, a transmitter 144, a test controller 142, aclock circuit 143 and a functional circuit 145. Receiver 140 has aninput 146 coupled to a predecessor integrated circuit 12 in the chain.Receiver 140 has outputs for a test clock signal TCK, a test mode signalTMS and a test data signal TDI and further outputs. The outputs for testclock signal TCK and test mode signal TMS are coupled to test controller142 and transmitter 144. Test controller 142 has a test data inputcoupled to the test data output of receiver 140 and a test data outputcoupled to transmitter 144. Transmitter 144 has an output 148 coupled toa successor integrated circuit in the chain. Functional circuit 145 iscoupled to the other integrated circuits 12 via functionalinterconnection circuit 16 and to test controller 142.

In operation in a test mode tester 10 outputs words of test data and/ortest instructions, combined with test clock signals and mode selectsignals to the chain of integrated circuits 12, 14 via output 18. Eachintegrated circuit 12, 14 receives the words of test data and/or testinstructions combined with test clock signals and mode select signalsfrom its predecessor in the chain and transmits words of test dataand/or test instructions combined with test clock signals and modeselect signals to its successor. In integrated circuit 14 receiver 140receives words of successive bits of information from input 146 anddecodes a test clock signal TCK, a mode select signal TMS, an input databit TDI and optional further bits from each word. Receiver 140 appliesthe test clock signal TCK, the mode select signal TMS and the input databit TDI to test controller 142. Test controller 142 may be aconventional IEEE1149.1 test controller. Test controller 142 passessignals to functional circuit 145, for example to shift test datathrough a shift register chain, to update data in flip-flops that outputtest data to functional interconnect circuit 16, or to capture responsesignals from functional interconnect circuit 16. Test controller 142outputs a test data output bit, which is typically either a bit that hasbeen previously received as a test data input bit or a bit of responsedata captured from functional circuit 145 or from functionalinterconnect circuit 16.

Transmitter 144 receives the test clock signal TCK, the mode selectsignal TMS from receiver 140 and the test data output bit from testcontroller 142. Transmitter 144 combines the test clock signal TCK, themode select signal TMS from receiver 140 and the test data output bittogether with the optional further bits into a word that is transmittedserially to a successor in the chain of integrated circuits 12, 14.Thus, transmitter 144 combines the test clock signal TCK and the modeselect signal TMS will be transmitted from integrated circuit 14generally with one word delay after reception from the integratedcircuit 14.

Clock circuit 143 reconstructs a clock signal from the signalstransmitted via serial input 146 for clock receiver 140 and transmitter144. The clock signal is used for decoding and encoding serial data inreceiver 140 and transmitter 144. As an alternative, handshaking may beused between the transmitter and receiver of successive integratedcircuits 12, 14, but this requires more connections.

As a result the test clock signal TCK, the mode select signal TMS fromreceiver 140 and the test data output bit are transferred between eachpair of successive integrated circuits 12, 14 in the chain, and used inparallel inside the integrated circuits 12, 14. Because all these testsignals are transmitted through a single chain of integrated circuit noclock skew problems arise.

The test controllers 142 of the different integrated circuits in thechain are designed to operate in cooperation with each other, allstepping through a same, selectable series of test states and passingtest data or instructions to integrated circuits further down the chainor passing response data from integrated circuits in the preceding partof the chain. The test clock signal and the test mode select signalcontrol the states assumed by the test controllers, for example using astate diagram compatible with the IEEE1149.1 test standard. The statediagram defines, among others, update and capture states. In response toreaching the update state test controller 142 commands update flip-flops(not shown separately) to copy test data or instruction data receivedvia the chain in order to output the test data or instruction data. Inresponse to reaching the capture state test data is loaded for shift outthrough the chain.

Tester 10 controls when a word with a new test clock signal value istransmitted through the chain. Preferably the word with the old clocksignal value is repeated until the word with the new test clock signalvalue is transmitted. This permits clock circuit 143 to remain locked tothe bit rate and reduces the effect of missed words.

Generally, tester will transmit a word with a new clock signal valueafter a delay, corresponding for example to a series of N words with theold clock signal value. The delay is selected so that a minimum timeinterval from update to corresponding capture by different integratedcircuits is preserved, as well as a minimum time interval from captureto next update. That is, before tester 10 outputs a word with a newclock signal value that will cause an update, a word with the clocksignal value that causes the preceding capture must have arrived at thelast integrated circuit in the chain, so that all integrated circuitswill have executed the capture. Vice versa, before tester 10 outputs aword from a next series with a next different test clock signal valuethat will cause a capture, a word with the clock signal value thatcauses the preceding update must have arrived at the last integratedcircuit in the chain, so that all integrated circuits will have executedthe capture.

Various techniques may be used to ensure that the delay during which thetest clock signal does not change is sufficient to ensure the existenceof such a time interval. In one embodiment, tester 10 monitors wordsreceived from the chain at input 19 and decodes the test clock signalreceived from these words. In this embodiment tester 10 changes theclock signal in the words at output 18 only once tester 10 detects thatthe previous change of the clock signal has arrived at input 19. Thus itis ensured that there will always be a time interval in which allintegrated circuits 12, 14 are in the same state, which ensures propersequencing of updates and captures. In a more aggressive embodimenttester 10 at least delays outputting of words with a new clock signalthat causes transitions to update or capture states until a word withthe clock signal transition after a preceding capture and update hasbeen received at input 19 respectively.

In another embodiment, a programmed value of the delay (e.g. of thenumber of words N that must be repeated) may be used as appropriate fora circuit 11 under test, or a required value of the delay may bedetermined once for a number of series of words from a measurement ofthe delay of the chain of a circuit under test.

Although FIG. 1 assumes that all integrated circuits 12, 14 in the chainreceives synchronization information such as a clock signals and/or amode select signal through the chain, this is not in fact necessary.Without deviating from the invention one or more further integratedcircuits may be added to the chain that receive a centralsynchronization information from the tester. For example such furtherintegrated circuit may be included at the front of the chain, receivingtheir clock signals etc. centrally from tester 10. In this case the lastintegrated circuit preferably is arranged to generate and supply wordswith synchronization information and data, results or commands to theremainder of the chain, from the centrally received synchronizationinformation and its local data, results or commands. When the centralsynchronization information can be passed to this part of the integratedcircuits with little skew this still permits a high test speed.

In another alternative a local group of a plurality of successivecircuits in the chain may in common receive local synchronizationinformation from a local synchronization information supply circuit. Inthis case the local synchronization information supply circuit derivessynchronization from the chain at the start of the group and suppliesthis derived synchronization information (e.g. a test clock signal) tothe integrated circuits of the local group. Preferably, a localsynchronization passing circuit combines data, results and commandoutput at the end of the chain with the locally generatedsynchronization information and passes the combined information throughthe chain to further integrated circuits.

Thus an “island” of conventional centrally test clocked integratedcircuits may be incorporated in the chain. Effectively, the “shell”created around test controller 142 in one integrated circuit 14 in thiscase extends around a plurality of conventional integrated circuits. Thelocal synchronization information supply circuit and the localsynchronization passing circuit that interface to the remainder of thechain have functions similar to receiver 140 and transmitter 144 and maybe incorporated in integrated circuits at the start and end of theisland, or even in one integrated circuit that is included at twopositions in the chain at the start and end of the island. When theintegrated circuits in the island can be clocked with little skew, testspeed is still high.

FIG. 2 shows a more detailed embodiment of an integrated circuit. Theintegrated circuit has an external test reset signal input TRSTN coupledto test controller 142. The reset inputs of different integratedcircuits are generally coupled in common to a central reset source, thatis, not through a chain structure. The integrated circuit has adifferential test signal input 200 and a differential test signal output218. Furthermore, the circuit contains an input sense amplifier 202, aninput shift register 204, an input decoder 206, an input latch 208, inseries between differential input 200 and test controller 142. An outputencoder 212, an output shift register 214 and an output driver 216 arecoupled between test controller 142 and differential output 218. Outputsof input latch 208 for a test clock signal and a test mode select signalare coupled to output encoder directly, in parallel with test controller142.

In addition to clock circuit 143 an external clock input TCK isprovided. An output of clock circuit 143 and clock input TCK are coupledto inputs of a multiplexer 224. An output of multiplexer 224 is coupledto clock inputs of input shift register 204 and input latch 206, thelatter via a counter 226 and an enable circuit 229. Enable circuit 229has an enable input coupled to an error signal output of input decoder206. The output of multiplexer 224 is coupled to a shift clock input ofoutput shift register 214 and to a load input of output shift register214, the latter via a count and delay circuit 242. Multiplexer 224 andclock circuit 143 are controlled by a control register 225, which is infact part of test controller 142, but is shown separately for the sakeof clarity.

In operation, test controller 142 is initially reset to a reset stateusing reset input TRSTN. During operation the words with the test clocksignal, the test mode signal and the test input data arrive atdifferential input 200. Successive bits of the words are sensed andloaded into input shift register 204. The bits are output in parallelfrom input shift register 204 to input decoder 206. Assuming that thenumber of bits per transmitted word is “n” (n=6 for example) a decodingresult is latched into input latch 208 from input decoder 206 every nclock cycles, provided that input decoder 206 indicates that no errorhas occurred. By way of example, input decoder 206 decodes five bitsfrom a six bits word using some error detecting code.

The bits latched into input latch 208 include a bit representing thetest clock signal, a bit representing the test mode select signal, a bitrepresenting the test data input and optional further bits. The testclock signal, the test mode select signal, and the test data input arefed to test controller 142 and used as conventional IEEE1149.1 testsignals TCK, TMS and TDI. In response to these signals test controllerproduces successive test data output signals (TDO), at successive TCKlevel transitions. The TDO signal typically derives either from anearlier TDI value or from a test result captured from circuit 11, forexample from functional interconnect circuit 16. Test controller 142continues outputting the same TDO value at least while TCK remains atthe same logic level.

Output encoder 212 receives TCK and TMS as well as optional further bitsfrom input latch 208 and TDO from test controller 142. Output encoder212 forms bits of an output word from these signals, typicallyperforming the inverse of the decoding performed by input decoder 206.The encoded bits are loaded into output shift register 214, preferablyat the same frequency as with which data is loaded into input latch 208(every n clock cycles), but with a delay of a number of clock cycles sothat the data is loaded into output shift register 214 with sufficientafter loading input latch 208, so that the TDO value corresponding tothe TCK and TMS values in that latch is available at the output of testcontroller 142. Output shift register 214 shifts the encoded bits todriver 216, which drives differential output 218.

Any desirable form of encoding and decoding may be used. For example aparity bit may be added to the test clock signal, the test mode selectsignal, the test data and the optional further bits. Similarly startand/or stop bits may be added, or other information that facilitatesidentification of word boundaries. In this case a word boundarydetection circuit may be used to detect word boundaries from theincoming bits and to control loading into input latch 208 and outputshift register 214. Similarly the encoding may be adapted to facilitatefrequency recovery from the transmitted data, for example by ensuring aminimum number of signal transitions in the words, and/or the encodingmay be adapted to service certain channel characteristics, for exampleby ensuring that there are as many bits of one value as of the oppositevalue.

Although input decoder 206 and output encoder 212 are shown withoutclock input, it will be appreciated that clocked decoders and/orencoders may be used, for example for computing parity by exoring astored intermediate parity successive with successive incoming bits.

Clock multiplexer 224 makes it possible to choose between using anexternal clock and an internal clock from clock circuit 143. Theexternal clock is preferably supplied to al integrated circuits 12, 14in parallel, that is, not via a chain structure but from a centralsource, for example in tester 10. This limits the maximum usableexternal clock value to a much lower value than that of clock circuit143. After reset, the external clock is selected. At this stage tester10 supplies test data through the chain at the frequency of the externalclock. At this stage the external clock is used to initialize theintegrated circuits and in particular to load control register 225 withinstruction data supplied via input 200. The instruction data sets thenominal frequency of clock circuit 143 and commands clock multiplexer224 to switch to the internal clock circuit 143. Subsequently thecontent of control register 225 generally remains unchanged during thetest, but it may be updated using instruction data received undercontrol of clock circuit 143.

However, it should be appreciated that the initial use of an externalclock is merely a convenient solution, to ensure initialization. Withoutdeviating from the invention the clocks signals may initially besupplied through the chain as well at a low bit rate so that allintegrated circuits are capable of handling the bit rate.

FIG. 3 shows an integrated circuit with a programmable memory 30, foruse in the chain of circuit 11 of FIG. 1. The outputs for further bitsfrom the words received via test input 146 are coupled to memory 30, aswell as the output for the incoming test data. In the embodiment of FIG.3 memory 30 is clocked by the test clock signal derived from thereceived words. In operation, memory 30 is programmed using datasupplied as test data. After transmitting a memory word of data (e.g. 16bits) the further bits are used to generate a write enable pulse tocause the received data to be written into memory 30. Successive levelsof the write enable signal may be encoded in words with successive clocksignal values. This has the advantage that programming of the memory canbe controlled by the test signals and that transmission of the furtherbits is not affected when certain integrated circuits do not copy allwords to their output.

In principle new write enable signals may be supplied in every new word,even if the test signals, such as TCK and TMS remain unchanged in thenew words. Thus memory 30 can be programmed quickly.

FIG. 3 a shows an embodiment in which new data that has to be written isbe supplied in every word transmitted via the chain, clocked by clockcircuit 143 instead of by the received test clock signal. This speeds upprogramming. If the data is included as test data, which is alsosupplied to test controller 142, this may be incompatible with theoperation of test controller 142, in this case test controller 142 ispreferably switched to a state where this has no effect during memoryprogramming. In an alternative, data to be programmed into memory 30 maybe supplied as further bits from the received words.

FIG. 4 shows an integrated circuit with partially independent clockcircuits 40, 42 for input and output of words with test signals. Bothclock circuits 40, 42 derive their clock signals from a retrieved clocksignal from clock circuit 143. The clock frequencies output by the clockcircuits 40, 42 are independently programmable using control register225. Clock circuits 40, 42 control the bit rates of reception andtransmission at input 146 and output 148 respectively. In operation thispermits use of a circuit 11 with integrated circuits capable ofoperating at disparate speeds. Different parts of the chain may passwords at different clock rates, under control of frequencies programmedinto the control register 225 of different integrated circuits in thechain. Preferably, a delayed disable circuit 44 is included to ensurethat a word for transmission is latched into transmitter 144 with apredetermined delay after a new word has been output from receiver 140,so as to permit controller 142 to output a test data output signal inresponse to the new word before the word for transmission is latchedinto transmitter 144. For this purpose, a signal indicating output of anew word is preferably supplied from receiver 140 to transmitter 144 viadisable circuit 44, to block latching of a new word at transmitter 144for a predetermined number of clock periods of clock source 143 afterreception and output of a new word by receiver 140.

By using different programmable clock frequencies the delay experiencedby the test signals when they travel through the chain can be minimized,by having pairs of successive integrated circuits in the chain operateat or near the minimum of the maximum possible speeds of the respectiveintegrated circuits of the pair. Given the integrated circuits used incircuit 11 under test, it can readily be determined which clock speedsmay be used. The selected frequencies are then encoded in frequencyprogramming data transmitted by tester 10 via the chain, to load thefrequency programming data into control register 225. Because the delaywith which test signals such as TCK travel through the chain is thusminimized, the frequency with tester 10 may change the test signals canbe increased. It will be understood that a similar increase in speed canbe realized by using asynchronous handshakes between the integratedcircuits in the chain, but for this more input pins will generally berequired.

Although clock circuits 40, 42 are shown to use a common clock source143, it will be understood that output clock circuit 42 may becompletely independent. In this case, it measures to control transferbetween different clock domains may be needed. In yet another embodimenthandshake signals may be used to transfer data from the words betweendifferent integrated circuits and inside the integrated circuits. Inthis case, no clock programming is needed to achieve optimal speed.

FIG. 4 a shows a further embodiment, wherein multiplexers 46, 48, 49have been added to permit selection between using internal clock 143 andan external clock input, for connecting the integrated circuits incommon to an central external test clock source. Multiplexers 46, 48, 49are controlled by command data from control register 225. Thus, it ispossible to use a central clock initially and to switch to clockinformation that has been passed through the chain later.

In another embodiment strobe signals may be used between the integratedcircuits to permit clock recovery. Strobe signals are known per se. Forexample a strobe signal and a data signal may be selected so the strobesignal makes a transition when data from the words to be transmitted islogic one and the data signal makes a transition when the data to betransmitted is logic zero. In this case the recovered clock is theexclusive or of the data and strobe signal. This permits a high datarate for relatively low strobe and data signal bandwidths. At intervals,the coding may change to mark word boundaries through phase jumps in therecovered clock signal.

Although the invention has been described in terms of the IEEE1149.1standard, using conversion of words transmitted through a chain ofintegrated circuits to recover test clock signals and test mode selectsignals as well as test data, it will be understood that the inventionis not limited to the application to IBEE1149.1. Other test protocolsmay be used. Similarly, although an advantageous embodiment effectivelyadds a shell around a test controller that treats certain test signals,such as TCK and TMS, as centrally supplied signals, so that the shellretrieves these signals from signals supplied through a chain, it willbe appreciated that other embodiments are possible, in which the chainedtransmission of these signals is not hidden from test controller.

As shown, the test synchronization signals TCK, TMS are transmitted aspart of words that are transmitted bit serially. As an alternative, oneor more of these signals may be transmitted in parallel through thechain. By using the same chain, clock skew problems are avoided. Serialtransmission, however, has the advantage of reducing the number of inputterminals that must be provided for test purposes, without undulydecreasing test speed, because the test speed is ultimately determinedby the fact that the synchronization signals change only at a rateneeded to ensure that capture and update of different integratedcircuits in the chain occurs in the correct order. Thus, transmission ofseveral signals serially does not significantly affect speed.

As also shown, only one bit of test data is included in each word, sothat only one bit is loaded into test controller 142 and output fromcontroller when the test synchronization signals, such as TCK and TMS,change. This is compatible with IEEE1149.1. In an alternative embodimentthe words contain more than one test data bit, the data bits from a wordbeing loaded into test controller 142 or output from test controller 142in parallel.

As also shown, the test data is made to change only when the testsynchronization signals, such as TCK and TMS, change. As an alternative,the test data may change more frequently, so that successive words thatcontain the same TCK and TMS bits contain different TDI or TDO bits.

FIG. 5 shows an integrated circuit that makes use of more frequentchanges of test data. The integrated circuit contains a shift register50 which may be any one of the shift registers for TDI/TDO data used inIEEE1149.1 for example. An output of receiver 140 for outputting testdata TDI is coupled to an input of shift register 50. An output of shiftregister 50 is coupled to transmitter for supplying test bits fortransmission of test data TDO. In a further embodiment more than onetest data bit may be loaded into shift register 50 in parallel or outputfrom shift register 50 in parallel per data word.

Shift register 50 receives clock signals from clock circuit 143 viaclock supply circuit 52. Thus, data is shifted through shift register 50at a higher rate than the rate of test clock signal TCK. Apart from itsinput and output and clocking, shift register is controlled using theinternal test synchronization signals (TCK and TMS) that have beenrecovered. These synchronization signals control for example updatingwith data from shift register 50 and capture into the shift register 50.

In an embodiment clock supply circuit 52 passes clock pulses at adivided clock rate so that for each word received at input 146 one clockpulse is passed. However, when it is not the case that new test data issupplied in each successive word clock supply circuit 52 may furtherreduce the number of passed clock pulses, for example to one clock pulsefor every two words if every second word contains a new test data bit.In a further embodiment, tester 10 may include information, such as abit counter, in the words to indicate whether the word contains new testdata. In this case this information is used to control whether clocksupply circuit passes a clock pulse.

The embodiment of FIG. 5 permits more frequent changes of test data thansynchronization data such as TCK and TMS. This has the advantage thatmore test data can be transmitted per test clock TCK period. However,this may lead to problems when the chain contains some integratedcircuits that are slower than others. In this case words are preferablyexchanged at a higher rate between fast integrated circuits in the chainand at a lower rate with slower circuits. Thus, fewer successive wordswith the same synchronization information are exchanged with slowerintegrated circuits than between faster integrated circuits. This maymake it unpredictable when test data is passed and when not when thetest data changes more frequently than the synchronization information.In an embodiment therefore, the test data changes only when thesynchronization data to ensure complete transmission of test data in asimple way.

1. An electronic circuit comprising: a plurality of integrated circuits, each comprising a test control circuit, switchable between a test mode and a normal operating mode; functional connections between the integrated circuits; test communication connections in addition to the functional connections and forming a chain that includes the integrated circuits, the integrated circuits being arranged to receive and transmit, from one integrated circuit to another successively through the chain, test data, test results and/or commands together with synchronization information, for timing output of the test data to the functional connections and capture of the test results from the functional connections.
 2. An electronic circuit according to claim 1, wherein each integrated circuit in the chain is arranged to step through a series of states, wherein successive states are selectable under control of the synchronization information indiscriminately for all integrated circuits in the chain, the states determining sequencing of update and capture.
 3. An electronic circuit according to claim 1, wherein the integrated circuits are arranged to transmit the synchronization information temporally in series with the test data, test results and/or commands through a same communication conductor from one integrated circuit to another in the chain.
 4. An electronic circuit according to claim 3, wherein each integrated circuit in the chain receives and transmits successive words that contain the synchronization information temporally in series with the test data, test results and/or commands, the integrated circuits being arranged to copy the synchronization information received from a received word to a transmitted word and to replace a received bit of the test data, test results and/or commands from the received word in the transmitted word by an internal bit of the test data, test results and/or commands, produced in the integrated circuit.
 5. An electronic circuit according to claim 3, wherein at least one of the integrated circuits comprises a test controller circuit with parallel inputs for at least a bit of the synchronization data and a bit of the test data, test results and/or commands respectively, the at least one of the integrated circuits being arranged to update substantially simultaneously parallel supply to the test controller of the bit of synchronization data and the bit of the test data, test results and/or commands received serially via the chain.
 6. An electronic circuit according to claim 1, wherein at least part of the integrated circuits contains an internal clock circuit for controlling programmable bit rates of reception and transmission of synchronization information and the test data, test results and/or commands, the bit rate of reception and transmission being at least partly independently programmable, the integrated circuits in said part being arranged to set the bit rate to a predetermined value in an initial state, and to reprogram one or more of the bit rates under control of an command received via the chain specifically for the integrated circuit.
 7. An electronic circuit according to claim 6, wherein the integrated circuits of said at least part of the integrated circuits each have a clock input terminal, the clock input terminals being coupled in common to a test clock input of the electronic circuit, the integrated circuits of said at least part being arranged to derive the bit rate from the clock input terminal in the initial state, and from the clock circuit upon receiving a command to do so via the chain.
 8. An electronic circuit according to claim 6, wherein the integrated circuits of said at least part of the integrated circuits each have an external reset input terminal, the reset input terminals being coupled in common to a test reset input of the electronic circuit, the reset terminals of the integrated circuits of said at least part being arranged reset the integrated circuit to the initial state in response to a reset signal at the reset terminal.
 9. A test system comprising: An electronic circuit comprising: A plurality of integrated circuit, each comprising a test control circuit, switchable between a test mode and a normal operation mode; Functional connections between the integrated circuits; Test communication connections in addition to the functional connections and forming a chain that includes the integrated circuits, the integrated circuits being arranged to receive and transmit, from one integrated circuit to another successively through the chain, test data, test results and/or commands together with synchronization information, for timing output of the test data to the functional connections and capture of the test results from the functional connections; and A tester coupled to an input and an output of the chain for supplying the test data and/or commands and for receiving the test results, wherein the tester is arranged to adjust a time interval after which the synchronization at the input is updated, dependent on a determination of a delay incurred by the synchronization information when the synchronization information travels through the chain, so that synchronization information that triggers the update arrives at the output of the chain before synchronization that triggers capture as applied at the input of the chain.
 10. An integrated circuit, comprising: a test control circuit, switchable between a test mode and a normal operating mode; functional connections for connecting to external circuits; a test input and a test output in addition to the functional connections, the integrated circuit being arranged to receive test data, test results and/or commands together with synchronization information at the test input, for timing output of the test data to the functional connections and capture of the test results from the functional connections, and to transmit test data, test results and/or commands together with synchronization information at the test output.
 11. An integrated circuit according to claim 10, arranged to receive and transmit the synchronization information temporally in series with the test data, test results and/or commands through a same input communication conductor and a same output communication conductor respectively.
 12. An integrated circuit according to claim 11, arranged to receive and transmit successive words that contain the synchronization information temporally in series with the test data, test results and/or commands, the integrated circuit being arranged to copy the synchronization information received from a received word to a transmitted word and to replace a received bit of the test data, test results and/or commands from the received word in the transmitted word by an internal bit of the test data, test results and/or commands, produced in the integrated circuit.
 13. An integrated circuit according to claim 12, comprising a programmable circuit such as a programmable memory, the words containing one or more positions in addition to positions for the synchronization information and the test data, test results and/or commands, for transmitting programming information for programming the programmable circuit, the programmable circuit being coupled to receive the programming information from the chain.
 14. An integrated circuit according to claim 12, arranged to receive and transmit the words, copying information from one or more positions in addition to positions for the synchronization information and the test data, test results and/or commands from received words to transmitted words.
 15. An integrated circuit according to claim 12, arranged to step through a series of states, wherein successive states are selectable under control of the synchronization information, the states determining sequencing of update and capture.
 16. An integrated circuit according to claim 11, wherein the test controller circuit has parallel inputs for a bit of synchronization data and a bit of the test data, test results and/or commands respectively, the synchronization information clocking processing of the bit of the test data, test results and/or commands, the integrated circuit comprising a shell supplying the bit of synchronization data and the bit of the test data, test results and/or commands received serially in parallel to the parallel inputs.
 17. An integrated circuit according to claim 10, comprising a communication clock circuit for controlling programmable bit rates of reception and transmission of synchronization information and the test data, test results and/or commands, the bit rate of reception and transmission being at least partly independently programmable, the integrated circuit being arranged to set the bit rate to a predetermined value in an initial state, and to reprogram the bit rates under control of an integrated circuit specific command received via the chain.
 18. An integrated circuit according to claim 17, having an external clock input terminal, the integrated circuit being arranged to derive the bit rate from the clock input terminal in the initial state, and from the clock circuit upon receiving a command to do so via the test input.
 19. An integrated circuit according to claim 17, having an external reset input terminal, the integrated circuit being arranged reset to the initial state in response to a reset signal at the reset terminal.
 20. A method of testing an electronic circuit that comprises a plurality of integrated circuits, interconnected by functional connections, the method comprising: Providing test connections in addition to the functional connections, the test connections connecting the integrated circuits in a chain of successive integrated circuits; Receiving and transmitting from one integrated circuit to another successively through the chain, test data, test results and/or commands together with synchronization information; and Timing output of the test data to a functional connection and capture of the test results form the functional connections in each integrate circuit with the synchronization information received through the chain.
 21. A method according to claim 20, comprising: providing each integrated in the chain with a state machine circuit, for stepping through a series of states, entry into respective ones of the states controlling update and capture respectively, the synchronization information controlling which states the state machine circuit steps to and when; copying the synchronization information that controls the states from one integrated circuit to another through the chain.
 22. A method according to claim 20, comprising transmitting the synchronization information temporally in series with the test data, test results and/or commands through a same communication conductor from one integrated circuit to another.
 23. A method according to claim 22, comprising: receiving and transmitting successive words that contain the synchronization information temporally in series with the test data, test results and/or commands, copying the synchronization information received from a received word to a transmitted word and to replace a received bit of the test data, test results and/or commands from the received word in the transmitted word by an internal bit of the test data, test results and/or commands, produced in the integrated circuit.
 24. A method according to claim 22, comprising internally converting the received synchronization information temporally in series with the test data, test results and/or commands as to simulate reception of the synchronization information in parallel with the test data, test results and/or commands.
 25. A method according to claim 22, comprising: initially using a common bit rate for communicating the transmission of synchronization information and the test data, test results and/or commands through the chain; sending a programming command through the chain to program a bit rate of a pair of successive integrated circuits in the chain; changing the bit rates for communicating the transmission of synchronization information and the test data, test results and/or commands the integrated circuits in the pair according to the command.
 26. A method according to claim 25, comprising initially clocking transfer of information through the chain using a central clock connected in parallel to the integrated circuits of the chain, programming the bit rates of the transfer using commands transmitted through the chain and switching to clocking under control of the synchronization information that is transmitted through the chain after said programming.
 27. A method according to claim 25, comprising resetting the integrated circuits to an initial state with said common bit rate using a central reset signal applied in parallel to the integrated circuits of the chain. 